1. Field of the Invention
The present invention generally relates to a semiconductor memory device and, more particularly to a multi-port memory suitable for use as an image memory.
2. Description of the Prior Art
In an image display apparatus in order to display image data of figures, characters, etc. composited by a computer onto a raster-scanning type CRT screen, a memory called a frame buffer is needed to store the image data. A dual-port memory is generally used as the memory for the above purpose, having a random access memory and a serial access memory. Furthermore, the dual port memory generally contains a random port for writing into the random access memory the image data formed by the computer which is to be generated at an optional position on the CRT. Additionally, the dual port memory contains serial port for transferring data of one line in the random access memory to the serial access memory and reading the consecutive data necessary for the display onto the CRT from the serial access memory.
The dual-port memory referred to above is disclosed, for instance, in "Nikkei Electronics", pp195-219, May 20, 1985 edition by Nikkei MacGrow Hill, i the structure as shown in FIG. 6. In FIG. 6, a random access memory 30 consists of memory cell array 1, a row decoder 6 and a column decoder 7. A serial access memory 31 consists of a serial data register 2 for storing data transferred from the memory cell array 1, a serial address counter 8 for counting serial clocks and a data selector 3 for selecting an arbitrary bit of data stored in the serial data register 2 according to respective outputs from the serial address counter 8.
Reference numerals 20-24 denote terminals of input/output signals and control signals to realize input/output means to the dual-port memory. More specifically, reference numerals 20-22 are signal terminals of the random port, i.e., an input/output terminal of random data, an input terminal of address signals and an input terminal of control signals, respectively. The control signals such as RAS, CAS, DT/OE and the like fed through the input terminal 22 are input to a controller 9, thereby controlling inside (i.e. internal) operations of the memory. On the other hand, signal terminals 23, 24 of the serial port indicate an input terminal 23 of serial clocks counted by the serial address counter 8 and an output terminal 24 of serial data through which serial data stored in the serial data register 2 is output.
Upon writing the image data into an arbitrary position of the memory array 1 from the random port, a row address and a column address for the memory array 1 are, through the address signal input terminal 21 in a time sharing manner, taken into the address buffers 4, 5 in accordance with control signals C1 and C2 from the controller 9 and input to the row decoder 6 and column decoder 7, thereby accessing the arbitrary position of the memory array 1. In the above manner, the image data input to the random data input/output terminal 20 is written into the position accessed.
Meanwhile, upon reading the image data from the memory array 1 to the random port, an arbitrary position of the memory array 1 is accessed to in the same manner as the aforementioned image data writing process position of the memory array accessed is determined in accordance with the control signals C1 and C2 from the controller 9.
In order to read the serial data from the serial port, a transfer gate 16 is controlled by a control signal G1 generated from controller 9 by control signals to the control signal input terminal 22, whereby the data of one line in the memory array 1 selected by the row address is transferred to the serial data register 2. The serial address input to the address signal input terminal 21 is loaded in the serial address counter 8. The data selector 3 selects and outputs the data at a bit position of the serial data register 2 designated by the output from the serial address counter 8 to the serial data output terminal 24. As the serial address counter 8 counts the serial clock cycles input through the serial clock input terminal 23, the position of the serial data register 2 selected by the data selector 3 moves sequentially to higher order bits, and accordingly the data of the serial data register 2 is sequentially read out.
FIG. 7 is a timing chart showing the serial data transfer and reading thereof. The input-signals to the control signal input terminal 22 are, a RAS signal for controlling the timing to input a row address, a CAS signal for controlling the timing to input a column address and a DT/OE signal for controlling the transfer of serial data. At a time t1 when RAS signal falls, a line address Al of the memory array 1 to transfer the serial data from the address signal input terminal 21, and a logic "0" signal as the DT/ OE signal indicating the transfer cycle of the serial data is input. As a result, a time t3 when the DT/OE signal rises, data of the selected line of the memory array 1 is transferred to the serial data register 2 through the transfer gate 16.
An address showing a starting position for reading from the serial data register 2 is loaded in the serial address counter 8 by an address A2 input at time t2 when the CAS signal falls. The serial data transferred to the serial data register 2 is sequentially read out in synchronization with the rising edge of the serial clock 23 which is input after time t3. In this case, a serial data C0, which is read out first is the data of the serial data register 2 at the position selected by the address A2 loaded in the serial address counter 8. Afterwards, the content in the serial data register 2 is sequentially read out as C1, C2, C3, . . . as the serial address counter 8 counts up in a synchronous manner with the serial clock cycles input through the serial clock input terminal 23.
Accessing the memory array through the random port is possible while the data is being read out from the serial data register 2, and this can be used for writing the image data into the memory array 1. Therefore, the imaging speed of the image data is improved.
However, various functions require the image display apparatus to achieve a multi-window display. That is, not only the image data of figures, characters and the like composited by a compute but also dynamic picture images such as video images, etc. are desired to be displayed on the same screen. Since the conventional dual-port memory is provided with the serial port having the serial data register in addition to the random port capable of accessing any arbitrary position of the memory array, if the dual-port memory is used for the image display apparatus, it is possible to substantially increase the time which an be allotted to write the data into the memory array 1 from the random port, while improving the describing speed. However, since the serial port is used exclusively to output the data onto the CRT and the memory itself does not provide a function which enables the continuous writing of data such as the dynamic image A considerably complicated circuit has to be installed outside the memory in order to display the dynamic images by the conventional image display apparatus.